An Integrated Hardware/Software Design Methodology for Signal Processing Systems

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http://hdl.handle.net/10138/298444

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Li , L , Sau , C , Fanni , T , Li , J , Viitanen , T , Christophe , F , Palumbo , F , Raffo , L , Huttunen , H , Takala , J & Bhattacharyya , S S 2019 , ' An Integrated Hardware/Software Design Methodology for Signal Processing Systems ' , Journal of Systems Architecture , vol. 93 , pp. 1-19 . https://doi.org/10.1016/j.sysarc.2018.12.010

Titel: An Integrated Hardware/Software Design Methodology for Signal Processing Systems
Författare: Li, Lin; Sau, Carlo; Fanni, Tiziana; Li, Jingui; Viitanen, Timo; Christophe, Francois; Palumbo, Francesca; Raffo, Luigi; Huttunen, Heikki; Takala, Jarmo; Bhattacharyya, Shuvra S.
Upphovmannens organisation: Department of Computer Science
Datum: 2019-02
Språk: eng
Sidantal: 19
Tillhör serie: Journal of Systems Architecture
ISSN: 1383-7621
DOI: https://doi.org/10.1016/j.sysarc.2018.12.010
Permanenta länken (URI): http://hdl.handle.net/10138/298444
Abstrakt: This paper presents a new methodology for design and implementation of signal processing systems on system-on-chip (SoC) platforms. The methodology is centered on the use of lightweight application programming interfaces for applying principles of dataflow design at different layers of abstraction. The development processes integrated in our approach are software implementation, hardware implementation, hardware-software co-design, and optimized application mapping. The proposed methodology facilitates development and integration of signal processing hardware and software modules that involve heterogeneous programming languages and platforms. As a demonstration of the proposed design framework, we present a dataflow-based deep neural network (DNN) implementation for vehicle classification that is streamlined for real-time operation on embedded SoC devices. Using the proposed methodology, we apply and integrate a variety of dataflow graph optimizations that are important for efficient mapping of the DNN system into a resource constrained implementation that involves cooperating multicore CPUs and field-programmable gate array subsystems. Through experiments, we demonstrate the flexibility and effectiveness with which different design transformations can be applied and integrated across multiple scales of the targeted computing system.
Subject: 113 Computer and information sciences
Referentgranskad: Ja
Licens: cc_by
Användningsbegränsning: openAccess
Parallelpublicerad version: publishedVersion


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