An Integrated Hardware/Software Design Methodology for Signal Processing Systems

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dc.contributor.author Li, Lin
dc.contributor.author Sau, Carlo
dc.contributor.author Fanni, Tiziana
dc.contributor.author Li, Jingui
dc.contributor.author Viitanen, Timo
dc.contributor.author Christophe, Francois
dc.contributor.author Palumbo, Francesca
dc.contributor.author Raffo, Luigi
dc.contributor.author Huttunen, Heikki
dc.contributor.author Takala, Jarmo
dc.contributor.author Bhattacharyya, Shuvra S.
dc.date.accessioned 2019-01-28T14:07:14Z
dc.date.available 2019-01-28T14:07:14Z
dc.date.issued 2019-02
dc.identifier.citation Li , L , Sau , C , Fanni , T , Li , J , Viitanen , T , Christophe , F , Palumbo , F , Raffo , L , Huttunen , H , Takala , J & Bhattacharyya , S S 2019 , ' An Integrated Hardware/Software Design Methodology for Signal Processing Systems ' , Journal of Systems Architecture , vol. 93 , pp. 1-19 . https://doi.org/10.1016/j.sysarc.2018.12.010
dc.identifier.other PURE: 121299571
dc.identifier.other PURE UUID: 78c5d1c1-a259-47dc-97c3-e65da004fdd3
dc.identifier.other WOS: 000460077100001
dc.identifier.other Scopus: 85059818575
dc.identifier.uri http://hdl.handle.net/10138/298444
dc.description.abstract This paper presents a new methodology for design and implementation of signal processing systems on system-on-chip (SoC) platforms. The methodology is centered on the use of lightweight application programming interfaces for applying principles of dataflow design at different layers of abstraction. The development processes integrated in our approach are software implementation, hardware implementation, hardware-software co-design, and optimized application mapping. The proposed methodology facilitates development and integration of signal processing hardware and software modules that involve heterogeneous programming languages and platforms. As a demonstration of the proposed design framework, we present a dataflow-based deep neural network (DNN) implementation for vehicle classification that is streamlined for real-time operation on embedded SoC devices. Using the proposed methodology, we apply and integrate a variety of dataflow graph optimizations that are important for efficient mapping of the DNN system into a resource constrained implementation that involves cooperating multicore CPUs and field-programmable gate array subsystems. Through experiments, we demonstrate the flexibility and effectiveness with which different design transformations can be applied and integrated across multiple scales of the targeted computing system. en
dc.format.extent 19
dc.language.iso eng
dc.relation.ispartof Journal of Systems Architecture
dc.rights cc_by
dc.rights.uri info:eu-repo/semantics/openAccess
dc.subject 113 Computer and information sciences
dc.title An Integrated Hardware/Software Design Methodology for Signal Processing Systems en
dc.type Article
dc.contributor.organization Department of Computer Science
dc.description.reviewstatus Peer reviewed
dc.relation.doi https://doi.org/10.1016/j.sysarc.2018.12.010
dc.relation.issn 1383-7621
dc.rights.accesslevel openAccess
dc.type.version publishedVersion

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