FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

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http://hdl.handle.net/10138/308152

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Roy , S S , Turan , F , Järvinen , K , Vercauteren , F & Verbauwhede , I 2019 , FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data . in 2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA) . International Symposium on High-Performance Computer Architecture-Proceedings , IEEE , New York , pp. 387-398 , International symposium on high performance computer architecture , Washington , United States , 16/02/2019 . https://doi.org/10.1109/HPCA.2019.00052

Title: FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
Author: Roy, Sujoy Sinha; Turan, Furkan; Järvinen, Kimmo; Vercauteren, Frederik; Verbauwhede, Ingrid
Contributor: University of Helsinki, Department of Computer Science
Publisher: IEEE
Date: 2019
Language: eng
Number of pages: 12
Belongs to series: 2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA)
Belongs to series: International Symposium on High-Performance Computer Architecture-Proceedings
ISBN: 978-1-7281-1444-6
URI: http://hdl.handle.net/10138/308152
Abstract: Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.
Subject: 113 Computer and information sciences
Cloud computing
privacy in cloud computing
homomorphic encryption
FV homomorphic encryption
latticebased cryptography
polynomial multiplication
number theoretic transform
domain specific accelerator
hardware accelerator
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