FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

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dc.contributor.author Roy, Sujoy Sinha
dc.contributor.author Turan, Furkan
dc.contributor.author Järvinen, Kimmo
dc.contributor.author Vercauteren, Frederik
dc.contributor.author Verbauwhede, Ingrid
dc.date.accessioned 2019-12-12T10:59:01Z
dc.date.available 2019-12-12T10:59:01Z
dc.date.issued 2019
dc.identifier.citation Roy , S S , Turan , F , Järvinen , K , Vercauteren , F & Verbauwhede , I 2019 , FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data . in 2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA) . International Symposium on High-Performance Computer Architecture-Proceedings , IEEE , New York , pp. 387-398 , International symposium on high performance computer architecture , Washington , District of Columbia , United States , 16/02/2019 . https://doi.org/10.1109/HPCA.2019.00052
dc.identifier.citation conference
dc.identifier.other PURE: 126029303
dc.identifier.other PURE UUID: 1e5532e4-e178-40ad-afed-95c3a7bd3cdb
dc.identifier.other WOS: 000469766300030
dc.identifier.uri http://hdl.handle.net/10138/308152
dc.description.abstract Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz. en
dc.format.extent 12
dc.language.iso eng
dc.publisher IEEE
dc.relation.ispartof 2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA)
dc.relation.ispartofseries International Symposium on High-Performance Computer Architecture-Proceedings
dc.relation.isversionof 978-1-7281-1444-6
dc.rights.uri info:eu-repo/semantics/openAccess
dc.subject 113 Computer and information sciences
dc.subject Cloud computing
dc.subject privacy in cloud computing
dc.subject homomorphic encryption
dc.subject FV homomorphic encryption
dc.subject latticebased cryptography
dc.subject polynomial multiplication
dc.subject number theoretic transform
dc.subject domain specific accelerator
dc.subject hardware accelerator
dc.title FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data en
dc.type Conference contribution
dc.contributor.organization Department of Computer Science
dc.description.reviewstatus Peer reviewed
dc.relation.doi https://doi.org/10.1109/HPCA.2019.00052
dc.relation.issn 1530-0897
dc.rights.accesslevel openAccess
dc.type.version acceptedVersion

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